The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, which is technology usable for a semiconductor device including an interconnection layer having a capacitor, for example.
The capacitor is an electronic element that accumulates charges therein, and, for example, used in a dynamic random access memory (DRAM). Such a capacitor may be required to have high capacitance. The capacitor has a larger capacitance with an increase in its surface area. Hence, the capacitor may be increased in surface area so as to have a larger capacitance.
On the other hand, a semiconductor chip is now required to have smaller area. When a capacitor is provided in such a semiconductor chip, the capacitor must have a small planar configuration. So, the capacitor may now be provided in a recess of an interconnection layer as described in, for example, Japanese Unexamined Patent Application Publication Nos. 2011-14731, 2004-342787, 2005-101647, 2011-54920, 2011-114049, 2012-160492, 2012-160493, 2013-55203, 2013-89712, and 2012-4533. Such a capacitor has a large surface area thanks to the inner side face of the recess, and has a small planar configuration.
In addition, Japanese Unexamined Patent Application Publication No. 2012-4533 (JP-A-2012-4533) describes the following capacitor. The capacitor is formed using a first recess provided on a surface of an interlayer dielectric film included in an interconnection layer, and a second recess provided on the bottom of the first recess. Specifically, the lower electrode of the capacitor is provided along the bottom and the side face of the second recess. The lower electrode is covered with a capacitive dielectric film and an upper electrode of the capacitor. Furthermore, a conductive plate is located over the upper electrode. The interlayer dielectric film has an interconnection provided in a region different from the region having the capacitor. The top of the interconnection is flush with the top of the conductive plate. JP-A-2012-4533 describes that such a structure improves flatness of the interconnection layer.